One of the important features of integrated circuits deigned for portable applications is their ability to efficiently utilize the limited capacity of the battery power source. Typical applications include cellular telephones and personal digital assistants (PDAs), which might have a Lithium ion battery or two AAA alkaline batteries as the power source. Users have come to expect as much as three to four weeks of standby operation using these devices. Standby operation refers to the situation where the cellular phone, handheld device, etc. is powered on but not being actively used (e.g., actively involved in a call). Generally, it is estimated that the integrated circuits providing the functionality of the device is only performing useful work approximately 2% of the time while the device is in standby mode.
Removing the power supply from selected circuits of a device during standby is a technique employed by designers for battery powered applications. The technique is generally applied only to circuit blocks outside of the central processing unit (CPU). A primary reason for not applying this technique to CPUs, has been the difficulty in being able to retain the current processor state information necessary to continue execution after coming out of the standby mode. One solution for this limitation involves saving the current processor state information to external storage mechanisms (e.g., such as flash memory, a hard disk drive, etc.). In such a case there is the overhead required in transferring the state to and from the external storage mechanism. Even if the battery powered device had a hard disk drive, and many don't, the time consuming state transfer may not meet the real time response requirements of the application when the device needs to wake up to respond to a new event.
Other issues are presented when the functionality of a device is implemented by a system-on-a-chip (SOC) integrated circuit. For example, when the core of a system-on-a-chip CPU is temporarily powered down (e.g., deep sleep mode), some of the outputs that connect to assorted peripherals (e.g. LCD display, SPI interface, SDIO, Hard-disk, etc.) should be held in an idle state to avoid having to reprogram the peripheral or lose existing context in the peripheral. This causes a problem since some peripherals need particular values to be set at their inputs (which are connected to the outputs of the SOC) to hold a safely inactive state. For example, if a device is connected to a SOC that is clocked on the falling edge of a clock signal, and the SOC is powered down with that signal as a logic 1, but the power down state is a logic 0 (e.g., ground), it will cause a spurious clock on that signal.
This problem is further exacerbated by the heavy use of pin-muxing or sharing, in which a single pin can have multiple functions in different designs by different customers. In one design a pin may be set to act as part of an SPI interface that wants to be held low when in sleep mode, while the same pin in another design, perhaps by a different customer may be used as a UART pin which would need to be held high when the CPU is put to deep sleep mode. While pin-muxing provides a way to put more features in each chip and allows the chip to be more suitable for a wide range of designs, it precludes knowing exactly at IC design time what each pin will be used for. A more flexible method of configuring the power down states is needed.
One solution to this problem would be to have a register for each pin that drives the pin to any one of the allowed number of states, such as: Input, output 0, output 1, output Hi-Z, open drain, etc. This is a workable solution, but has a problem that since normally the signals that control these functions come from the core of the SOC, they will not be present when the core is powered down in deep sleep mode. To overcome this, a second set of registers on the SOC on a special power domain (AO) which remains powered when the rest of the core is powered down in deep sleep mode is used to control the pins.
The special power domain allows the state information of these IO pads to be preserved. However the big problem is that it requires many signals from the portion of the chip that is in the special power domain to be routed to each pad. For example, with 300 signal pads and 3 wires per pad, as many as 900 traces have to be routed on the integrated circuit die, which is a large number at the top level of an integrated circuit die layout. These pad control signals must also be powered by the AO rail, which complicates the distribution of this AO rail or the routing of these pad control signals. The peripherals must be able to wake the processor from Deep Sleep mode when they assert an interrupt to be serviced.
The signals which must be powered by the AO domain require a significant number of routing and switching cells within the netlist design which must be configured for connection and powering by the AO domain. Conservatively, the signal routing cells are routinely coupled to the always on domain. This ensures that required signals that may be needed to wake the chip can be properly received and processed, or that state information of certain I/O pins be accurately retained for proper functioning. However, such conservative classification of signal routing cells as AO domain cells leads to a number of such cells being so classified, when they are actually not required for proper functioning. For example, some cells are configured to relay signals from a core domain, which is shutdown in sleep mode. There is no need for the cells to be powered when the core domain is shut down. Such misclassified cells simply lead to excessive leakage current and excessive power consumption.
Thus, what is needed is a solution enabling the powering down of a digital integrated circuit device for reduced standby power consumption while retaining the integrity of the operating state. What is further needed is a solution for identifying those cells of an integrated circuit netlist that do not need to be powered during sleep mode.